uart Project Status (11/02/2008 - 18:38:21)
Project File: uart.ise Current State: Synthesized
Module Name: uart_tx
  • Errors:
 No Errors
Target Device: xc3s500e-4fg320
  • Warnings:
 No Warnings
Product Version: ISE 10.1.02 - Foundation Simulator
  • Routing Results:
  
Design Goal: Balanced
  • Timing Constraints:
  
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
   
 
uart Partition Summary [-]
No partition information was found.
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slices 19 4656 0%
Number of Slice Flip Flops 13 9312 0%
Number of 4 input LUTs 37 9312 0%
Number of bonded IOBs 13 232 5%
Number of GCLKs 1 24 4%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent星期日 十一月 2 18:38:17 2008001 Info
Translation Report     
Map Report     
Place and Route Report     
Static Timing Report     
Bitgen Report     

Date Generated: 11/02/2008 - 18:38:21
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